Maxim-integrated Corona (MAXREFDES12) ZedBoard Manuel d'utilisateur télécharger pdf (Page 5)

Corona (MAXREFDES12#) ZedBoard Quick Start Guide

3. Included Files

The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for

Xilinx ISE version 14.2. The Verilog-based top.v module provides FPGA/board net

connectivity, allows HDL interaction with peripherals, and instantiates the wrapper that

carries both the Zynq Processing System and (I

C, SPI, GPIO, UART) soft peripherals

that interface to the Pmod ports. This is supplied as a Xilinx software development kit

(SDK) project that includes a demonstration software application to evaluate the Corona

subsystem reference design. The lower level c-code driver routines are portable to the

user’s own software project.

Figure 3. Block Diagram of FPGA Hardware Design

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Maxim-integrated Corona (MAXREFDES12) ZedBoard Manuel d'utilisateur Page 5