Maxim-integrated DS80C390 Manuel d'utilisateur Page 58
- Page / 58
- Table des matières
- MARQUE LIVRES
- DS80C390 1
- Dual CAN High-Speed 1
- Microprocessor 1
- DESCRIPTION 2
- ORDERING INFORMATION 2
- 3 of 58 110199 3
- PIN DESCRIPTION Table 1 4
- INT0 External Interrupt 0 5
- INT1 External Interrupt 1 5
- 80C32 COMPATIBILITY 7
- PERFORMANCE OVERVIEW 7
- INSTRUCTION SET SUMMARY 7
- SPECIAL FUNCTION REGISTERS 8
- 9 of 58 110199 9
- 40-BIT ACCUMULATOR 11
- MEMORY ADDRESSING 12
- INTERNAL MOVX SRAM 13
- EXTERNAL MEMORY ADDRESSING 13
- STRETCH MEMORY CYCLES 14
- EXTENDED STACK POINTER 15
- ENHANCED DUAL DATA POINTERS 16
- SYSTEM CLOCK CONTROL 17
- OSCILLATOR FAIL DETECT 18
- POWER MANAGEMENT MODE (PMM) 19
- SWITCHBACK 19
- IDLE MODE 20
- STOP MODE 20
- BAND-GAP SELECT 20
- RING OSCILLATOR 20
- TIMED ACCESS PROTECTION 21
- EMI REDUCTION 22
- PERIPHERAL OVERVIEW 22
- SERIAL PORTS 22
- WATCHDOG TIMER 22
- EXTERNAL RESET PINS 24
- INTERRUPTS 24
- INTERRUPT SUMMARY Table 12 24
- Register 7 6 5 4 3 2 1 0 28
- CAN INTERRUPTS 29
- ARBITRATION AND MASKING 29
- MESSAGE BUFFERING/OVERWRITE 30
- BIT TIMING 31
- ABSOLUTE MAXIMUM RATINGS* 32
- DC ELECTRICAL CHARACTERISTICS 32
- TYPICAL I 33
- VERSUS FREQUENCY 33
- 4CE0 − Valid to ALE Low 34
- 4CE0 − , 4PCE0− Valid to 35
- TIME PERIODS 36
- 37 of 58 110199 37
- 38 of 58 110199 38
- 3-PCE0 READ OR WRITE 39
- 3-CE0 READ 39
- 3-CE0 WRITE 40
- 44 of 58 110199 44
- RD Pulse Width 45
- RD Low to Valid Data In 45
- RD or WR Low 45
- RD or WR 45
- 46 of 58 110199 46
- 47 of 58 110199 47
- 54 of 58 110199 54
- WR signal 55
- 68-PIN PLCC 56
- 64-PIN LQFP 57
- DATA SHEET REVISION SUMMARY 58
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