Maxim-integrated High-Speed Microcontroller Manuel d'utilisateur Page 174
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High-Speed Microcontroller User’s Guide
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18. MICROCONTROLLER DEVELOPMENT SUPPORT
18.1 Technical Support
For technical support, go to https://support.maximintegrated.com.
18.2 Development Tools
Because the high-speed microcontroller family was designed for maximum compatibility with existing
8051 microcontrollers, users find that most of their existing 8051 tools work with our products.
.
18.3 Software Compatibility
Maxim microcontrollers execute the 8051 instruction set and are object code compatible with other 8051-
based products. The special features of Maxim microcontrollers are accessed via SFRs unique to our
products, but the devices do not use any new instructions. The new SFRs can be easily defined in the
user’s software with EQUATE statements or in a setup file. Once defined, these new SFRs receive the
same treatment as any of the original 8051 registers. This means that Maxim microcontrollers are
compatible with almost every 8051-based software tool available.
18.4 High-Level Language Compilers
Like assemblers, compilers must be informed of the existence and location of the SFRs unique to Maxim
microcontrollers. When using C, it is commonly necessary to identify the starting address for various
read/write segments such as XDATA and Stack. In addition, it is recommended that the large memory
model be used in conjunction with C compilers. This places the stack in off-chip SRAM. Microcontroller
systems usually have an abundance of such SRAM compared to ROM-based systems. While off-chip
stack results in slower execution time, the stack size becomes virtually unlimited.
To aid our customers, Maxim maintains a list of development tool vendors on its website at
www.maximintegrated.com/products/microcontrollers/8051/development_tools/proto.cfm. This page is
very useful when attempting to locate commonly used microcontroller aids such as compilers, test clips,
sockets, programmers, programming adapters, reference books, emulators, crystals and development boards.
- TABLE OF CONTENTS 2
- LIST OF FIGURES 7
- LIST OF TABLES 8
- 1. INTRODUCTION 9
- 2. ORDERING INFORMATION 10
- 3. ARCHITECTURE 11
- 3.1 ALU 11
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- 3.2.16 Interrupts 13
- 3.2.17 Timing Control 13
- 3.2.18 Real-Time Clock 13
- 3.2.19 Feature Summary 13
- 4. PROGRAMMING MODEL 14
- 4.1 Memory Organization 14
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- Figure 4-2. Register Map 16
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- Rev: 062210 23 of 176 23
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- 4.2.1 Port 0 (P0) 25
- 4.2.2 Stack Pointer (SP) 25
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- 4.2.8 Power Control (PCON) 27
- INT1 pin 28
- INT0 is level triggered 28
- Rev: 062210 29 of 176 29
- 4.2.11 Timer 0 LSB (TL0) 30
- 4.2.12 Timer 1 LSB (TL1) 30
- 4.2.13 Timer 0 MSB (TH0) 30
- 4.2.14 Timer 1 MSB (TH1) 30
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- 4.2.16 Port 1 (P1) 32
- RG bit 33
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- 4.2.21 Port 2 (P2) 36
- 7 6 5 4 3 2 1 0 37
- 4.2.25 Port 3 (P3) 38
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- RMS2, RMS1 42
- DME1, DME0 44
- LB3, LB2, LB1 44
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- CP/RL2 EXEN2 DCEN RESULT 46
- 4.2.36 Timer 2 Mode (T2MOD) 47
- 4.2.39 Timer 2 LSB (TL2) 48
- 4.2.40 Timer 2 MSB (TH2) 48
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- Rev: 062210 51 of 176 51
- 4.2.45 B Register (B) 52
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- Rev: 062210 57 of 176 57
- 4.3 Instruction Timing 58
- 4.4 Addressing Modes 59
- 4.4.2 Direct Addressing 60
- 4.4.4 Immediate Addressing 61
- 4.4.6 Relative Addressing 61
- 4.4.7 Page Addressing 61
- 4.5 Program Status Flags 62
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- 5.6 Instruction Timing 64
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- Memory Access 66
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- 22h 68
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- 5.7 Comparison to the 8051 71
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- Rev: 062210 73 of 176 73
- Rev: 062210 74 of 176 74
- Rev: 062210 75 of 176 75
- 6. MEMORY ACCESS 76
- 6.1 Internal Program Memory 76
- 6.2 Internal Data Memory 76
- 6.2.1 ROMSIZE Feature 77
- RMS2 RMS1 RMS0 78
- MAX ON-CHIP ROM 78
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- Rev: 062210 80 of 176 80
- 6.5 Data Memory Access 81
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- Rev: 062210 83 of 176 83
- 6.6 Data Memory Timing 84
- CKCON.2–0 85
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- C1 C2 C3 C4 87
- 7. POWER MANAGEMENT 88
- Precision Voltage Monitor 88
- 7.1.2 Power-Fail Reset 89
- 7.1.3 Power-On Reset 89
- 7.1.4 Bandgap Select 89
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- 7.1.5 Watchdog Wake-Up 91
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- 7.2 Power Conservation 93
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- 7.3 Power Management Modes 95
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- Rev: 062210 97 of 176 97
- 7.3.3 Switchback 98
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- Rev: 062210 100 of 176 100
- RG bit. The procedure to 101
- 8. RESET CONDITIONS 102
- 8.1 Reset Sources 102
- 8.2 Reset State 103
- 8.3 No-Battery Reset 103
- 8.4 In-System Disable Mode 104
- 9.1 Interrupt Overview 105
- 9. INTERRUPTS 105
- 9.2 Interrupt Sources 106
- 9.2.2 Timer Interrupts 107
- 9.2.4 Real-Time Clock 107
- 9.2.5 Power-Fail Interrupt 107
- 9.3 Simulated Interrupts 108
- 9.4 Interrupt Priorities 108
- 9.6 Interrupt Latency 109
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- Rev: 062210 111 of 176 111
- 10. PARALLEL I/O 112
- 10.1 Port 0 112
- 10.2 Port 2 113
- 10.3 Ports 1 and 3 114
- 10.4 Output Functions 115
- 10.6 Input Functions 115
- 10.9 I/O Port Timing 116
- 10.10 Optional Functions 117
- 11. PROGRAMMABLE TIMERS 118
- 11.1 16-Bit Timers 118
- INT1 and TR1 = 119
- 11.2 Mode 0 120
- 11.3 Mode 1 121
- 11.4 Mode 2 122
- 11.5 Mode 3 123
- 11.6 Timer 2 124
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- 11.7 Timer 2 Modes 126
- T2 = 1. As 127
- TIMER 2 128
- INTERRUPT 128
- T2CON.7 128
- 11.7.5 Baud-Rate Generator 129
- RL2 = 0 130
- 11.8 Time Base Selection 131
- 11.9 Watchdog Timer 132
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- Rev: 062210 135 of 176 135
- 12. SERIAL I/O 136
- 12.1 Serial Mode Summary 136
- 12.1.3 Mode 2 137
- 12.1.4 Mode 3 137
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- 12.3 Baud Rates 140
- 12.3.2 Mode 2 141
- 12.3.3 Mode 1 or 3 141
- 12.4 Serial I/O Description 143
- 12.4.2 Mode 1 145
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- RECEIVE TIMING 146
- TRANSMIT TIMING 146
- 12.4.3 Mode 2 147
- REGISTER 148
- 12.4.4 Mode 3 149
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- SADDR 11110000 151
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- 13. TIMED-ACCESS PROTECTION 153
- 13.1 Protected Bits 153
- 13.2 Protection Scheme 153
- TABLE_READ: 155
- 14. REAL-TIME CLOCK 156
- 14.3 Using the RTC Alarm 158
- TRMx bits must be 160
- 15. BATTERY BACKUP 161
- 15.1 Selecting a Battery 161
- REGISTER NAME LOCATION 162
- 16. INSTRUCTION SET DETAILS 163
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- MNEMONIC 165
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- 171 of 176 171
- 17. TROUBLESHOOTING 172
- 18.1 Technical Support 174
- 18.2 Development Tools 174
- 18.3 Software Compatibility 174
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- 2010 Maxim Integrated 176
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