Maxim-integrated Secure Microcontroller Manuel d'utilisateur Page 138
- Page / 187
- Table des matières
- DEPANNAGE
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Secure Microcontroller User’s Guide
138 of 187
The guaranteed preserved locations are areas in scratchpad RAM that will not be changed by the
bootstrap loader. These locations as useful for storing data such as serial numbers, which should be
retained regardless of the software. Similarly, the guaranteed destroyed locations have all been
overwritten during bootstrap loader execution with indeterminate data. These locations can be used to
store security-sensitive data, because it is erased by the loader before another program can read it out.
The indeterminate area contains various stacks and buffers used by the loader, and a given byte in this
area may or may not be modified by the loader. As such the user should not rely on the bootstrap loader
preserving any data in this area. In a like manner, because not all locations are used, the indeterminate
area of scratchpad RAM should not be used for storing security sensitive data.
16.2 Invoking the Bootstrap Loader on DS5000 Series Devices
The DS5000 is placed in its Program Load configuration by simultaneously applying a logic 1 to the RST
pin and forcing the
PSEN
pin to a logic 0 level. Immediately following this action, the DS5000 will look
for a serial ASCII carriage return (0DH) character received at 57,600, 19,200, 9600, 2400, 1200, or 300
bps over the serial port or a parallel program load pulse. For whichever type is first detected, the DS5000
will place itself in the associated Program Load mode. If an ASCII <CR> character is detected first, then
the DS5000 will place itself in the serial program load mode and will ignore any parallel program strobe
pulses. Conversely, if a parallel program strobe pulse is first detected, then the DS5000 will be placed in
the parallel program load mode and all incoming data on the serial port will be ignored. The selected
program load mode will remain in effect until the next time power is removed from the device or when
the program load configuration (RST = 1,
PSEN
= 0) is removed. The methods for invoking serial and
parallel modes were chosen to eliminate the possibility of accidentally invoking the opposite mode during
loading.
If the program load configuration is removed such that RST = 0 and
PSEN
= 1 with power still applied at
V
CC
, the device undergoes an internal hardware reset and will begin executing code from the reset vector
at 0000h in Program Memory.
16.3 Invoking the Bootstrap Loader on DS5001/DS5002 Series Devices
The DS5001 and DS5002 microcontrollers use an identical method to invoke the bootstrap loader. A
falling edge on the
PROG
pin will invoke the loader with a single device pin. Note that the
PROG
pin
must remain low for 48 oscillator clocks to be certain of recognition. Taking the
PROG
pin to a logic 1
will remove the loader and cause the DS5001 to perform a reset. Note also that the
PROG
pin must be
high for as much as 48 clocks before the CPU is guaranteed to exit the loader. This constitutes the
“pseudo-edge” detection of the program pin. Note also that pulling RST = 1 and
PSEN
= 0 will also cause
the loader to be invoked.
Once the loader mode stimulus has been detected, the microprocessor waits for an ASCII carriage return
(0Dh) characteristic on either the serial port or the RPC (8042) port. For serial reception, the loader will
auto-baud at 57600, 19200, 9600, 2400, 1200 and 300 bps. For RPC mode, the 0Dh value must be written
into the Data In buffer as described in the RPC section under Parallel I/O. When either of these conditions
is detected, the loader will place itself in that loader mode. Activity on the other port will be ignored. This
condition will remain until the loader is exited or power is cycled. When the loader stimulus is removed,
the processor will perform a hardware reset and begin execution at location 0000h.
- Rev 1/14 1
- TABLE OF CONTENTS 2
- 4 of 187 4
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1. INTRODUCTION 7
- 1.2 Software Security 7
- Separate Address/Data Bus 8
- Large Nonvolatile Memory 8
- In-System Loading 8
- High-Reliability Operation 8
- 1.3 Product Description 9
- 2. SELECTOR GUIDE 12
- 13 of 187 13
- Scratchpad Registers 14
- Serial I/O 14
- Programmable Timers 14
- 15 of 187 15
- Parallel I/O 16
- Program/Data RAM Interface 16
- High-Reliability Circuitry 16
- Software Encryption Logic 16
- Security Lock Logic 16
- Vector RAM 17
- Timed-Access Logic 17
- Watchdog Timer 17
- Resident Loader ROM 17
- 4. PROGRAMMER’S GUIDE 18
- 4.1.1 Internal Registers 19
- 21 of 187 21
- DS5000 SERIES MCON REGISTER 24
- Partition Table 25
- 29 of 187 29
- 30 of 187 30
- 32 of 187 32
- Figure 4-9. DS5000 SFR Map 34
- 35 of 187 35
- PCON, 087H 36
- Power Control Register 36
- Timer Control Register 37
- TCON, 088H 37
- Timer Mode Register 38
- TMOD, 089H 38
- Serial Control Register 39
- SCON, 098H 39
- Interrupt Enable Register 40
- IE, 0A8H 40
- Interrupt Priority Register 41
- IP, 0B8H 41
- DS5001 CRC Register 42
- CRC, 0C1H 42
- MCON, 0C6H 42
- 43 of 187 43
- PAA 43
- DS5001/DS5002 MCON Register 44
- Program Status Word Register 45
- PSW, 0D0H 45
- RPCTL, 0D8H 46
- RPS, 0DAH 47
- 4.9 Instruction Set 48
- 4.10 Addressing Modes 48
- 49 of 187 49
- 4.11 Program Status Flags 50
- 5. MEMORY INTERCONNECT 51
- DS5002FP 54
- 6. LITHIUM/BATTERY BACKUP 58
- 6.1 Data Retention 58
- Battery-Backed Circuits 58
- Battery-Attach Procedure 59
- Battery Lifetime 60
- Using Lithium Cells 61
- Freshness Seal 61
- 7. POWER MANAGEMENT 62
- 7.1 Idle Mode 62
- 63 of 187 63
- 7.2 Stop Mode 64
- 7.4 Power-Fail Interrupt 64
- 7.5 Total Power Failure 65
- 7.6 Partial Power Failures 66
- 8. SOFTWARE CONTROL 68
- 8.1 Timed Access 68
- Figure 8-1. Timed Access 69
- 8.2 Watchdog Timer 70
- 8.3 CRC Memory Verification 71
- 72 of 187 72
- Figure 8-2. CRC Code Example 73
- 9. FIRMWARE SECURITY 74
- Security Overview 74
- 9.1 Security Lock 74
- 9.2 RAM Memory 75
- 9.3 Encrypted Memory 76
- 77 of 187 77
- 9.4 Encryption Algorithm 78
- 9.5 Encryption Key 78
- 9.7 Dummy Bus Access 79
- 9.8 On-Chip Vector RAM 79
- 9.9 Self-Destruct Input 80
- 81 of 187 81
- Avoid Clear Text 82
- Avoid CRC or Checksum 83
- Use Random Values 83
- Change Code 83
- External Circuits 84
- Tamper Protection 84
- 10. RESET CONDITIONS 85
- 10.1 Reset Sources 85
- Reset Status Bits 85
- Table 10-A. SFR Reset States 86
- 10.1.1 Power-On Reset 87
- 10.1.2 No-V 88
- Power-On Reset 88
- 10.1.3 External Reset 88
- 10.1.4 Watchdog Timer Reset 88
- 10.2 Memory Map 89
- 10.3 Interrupts 90
- 10.4 Timers 90
- 91 of 187 91
- 11. INTERRUPTS 92
- 11.1 Interrupt Sources 92
- 11.2 External Interrupts 93
- 11.3 Timer Interrupts 93
- 11.4 Serial Port Interrupts 93
- 11.6 Simulated Interrupts 94
- 11.7 Interrupt Priorities 96
- 11.8 Interrupt Acknowledge 97
- 12. PARALLEL I/O 99
- 12.1 Output Functions 102
- 12.2 Input Function 103
- 12.5 RPC Interrupts 106
- 12.6 RPC Protocol 107
- 12.7 DMA Operation 107
- 108 of 187 108
- 13. PROGRAMMABLE TIMERS 109
- 13.1 Functional Description 109
- 110 of 187 110
- 13.2 Mode 0 111
- 13.3 Mode 1 111
- 13.4 Mode 2 112
- 13.5 Mode 3 114
- 14. SERIAL I/O 115
- 14.1 Function Description 115
- Serial Port Control Register 117
- 14.2 Baud Rate Generation 118
- 119 of 187 119
- 14.4 Asynchronous Operation 120
- 121 of 187 121
- 122 of 187 122
- 123 of 187 123
- 124 of 187 124
- Mode 2 and 3 125
- 126 of 187 126
- 127 of 187 127
- 128 of 187 128
- 15. CPU TIMING 130
- 15.1 Oscillator 130
- 15.2 Instruction Timing 131
- 132 of 187 132
- 136 of 187 136
- 16. PROGRAM LOADING 137
- 138 of 187 138
- 16.4 Exiting the Loader 139
- 142 of 187 142
- 16.8 Command Line Interface 143
- 16.9 Command Line Syntax 143
- Important Application Note 144
- 16.10 Command Summaries 145
- 146 of 187 146
- 147 of 187 147
- 16.11 Error Messages 148
- 16.12 Intel Hex File Format 149
- 152 of 187 152
- 153 of 187 153
- 154 of 187 154
- 17. REAL-TIME CLOCK (RTC) 155
- 17.1 DS5000T/DS2250T RTC 155
- 156 of 187 156
- 17.3 Registers 160
- 17.4 Special Bits 160
- 17.5 DS2251T/DS2252T RTC 162
- 17.6 Memory Map 163
- 165 of 187 165
- 166 of 187 166
- 168 of 187 168
- 169 of 187 169
- 170 of 187 170
- 171 of 187 171
- 172 of 187 172
- 173 of 187 173
- 174 of 187 174
- 175 of 187 175
- 18. TROUBLESHOOTING 176
- 177 of 187 177
- 178 of 187 178
- 18.7 Do’s and Don’ts 179
- 180 of 187 180
- 19. INSTRUCTION SET DETAILS 181
- MNEMONIC 183
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