
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
114
1-WIRE INTERRUPT
ENABLE BITS
TBE
OW_LOW
OW_SHORT
RSRF
RBF
TEMT
PD
IE5
Figure 9-1. 1-Wire Interrupt Source
ADDENDUM TO SECTION 9: INTERRUPTS
Unless marked, all flags must be cleared by the application software.
1
Cleared automatically by hardware when the service routine is entered.
2
If edge-triggered, the flag is cleared automatically by hardware when the service routine is entered. If level-triggered, the flag follows the state of the interrupt pin.
3
The global 1-Wire interrupt enable bit (EOWMI) and individual 1-Wire interrupt source enables are located in the internal 1-Wire registers and must be accessed by the
OWMAD and OWMDR SFRs. Individual 1-Wire interrupt source flag bits located in the internal 1-Wire bus master interrupt flag register are accessed in the same way.
PRIORITY CONTROL
BIT
PFI Power-fail interrupt 33h 0 PFI(WDCON.4)
N/A
INT0 External interrupt 0 03h 1 IE0(TCON.1)
2
EX0(IE.0) PX0(IP.0)
TF0 Timer 0 0Bh 2 TF0(TCON.5)
1
ET0(IE.1) PT0(IP.1)
INT1 External interrupt 1 13h 3 IE1(TCON.3)
2
EX1(IE.2) PX1(IP.2)
TF1 Timer 1 1Bh 4 TF1(TCON.7)
1
ET1(IE.3) PT1(IP.3)
TI0 or RI0 Serial port 0 23h 5
RI_0(SCON0.0),
TI_0(SCON0.1)
ES0(IE.4) PS0(IP.4)
Timer 2 2Bh 6 TF2(T2CON.7) ET2(IE.5) PT2(IP.5)
TI1 or RI1 Serial port 1 3Bh 7
RI_1(SCON1.0),
TI_1(SCON1.1)
ES1(IE.6) PS1(IP.6)
INT2
INT3
INT4
1-Wire bus master
interrupt
43h 8
IE2 (EXIF.4),
IE3 (EXIF.5),
IE4 (EXIF.6),
IE5 (EXIF.7)
3
EX2–5 (EIE.0)
EOWMI
3
PX2–5 (EIP.0)
TF3 Timer 3 4Bh 9 TF3 (T3CM.7) ET3 (EIE.1) PT3 (EIP.1)
TI2 or RI2 Serial port 2 53h 10 IE4 (EXIF.6) ES2 (EIE.2) PS2 (EIP.2)
WPI
EWPI (EIE.3) PWPI (EIP.3)
C0I CAN 0 interrupt 6Bh 12 Various C0IE (EIE.6) C0IP (EIP.6)
EAI Ethernet activity 73h 13
TIF (BCUC.5),
RIF (BCUC.4)
EAIE (EIE.5) EAIP (EIP.5)
WDTI Watchdog timer 63h 14
EWDI (EIE.4) PWDI (EIP.4)
EPMI
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