Maxim-integrated DS4830 Optical Microcontroller Manuel d'utilisateur

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

DS4830 User’s Guide 10 Figure 1-1 DS4830 Block Diagram This document is provided as a supplement to the DS4830 IC data sheet. This user’s guide

DS4830 User’s Guide 100 edge is used to sample the serial shift data. The Clock Phase Select (CKPHA; SPICF.1) bit controls whether the active or in

DS4830 User’s Guide 101 12.1.2 – SPI Character Lengths To flexibly accommodate different SPI transfer data lengths, the character length for any t

DS4830 User’s Guide 102 12.2.3 – Write Collision While Busy A write collision occurs if an attempt to write the SPIB data buffer is made during a t

DS4830 User’s Guide 103 12.4 – SPI Master The DS4830 has the following SPI interface signals. Functional name External pin name MSPIDI: Input to s

DS4830 User’s Guide 104 Figure 12-4: SPI Master Pin Configurations with mode fault enable and disable In master mode, the MSPICS pin of the master

DS4830 User’s Guide 105 12.4.3 – SPI Master Register Descriptions SPI Master Module has four SFR registers. These are SPICN_M, SPICF_M, SPICK_M an

DS4830 User’s Guide 106 12.4.3.2 – SPI Configuration Register (SPICF_M) SPICF_M Register Address: M5 [13h] Bit 7 6 5 4 3 2 1 0 Name ESPII SAS - -

DS4830 User’s Guide 107 12.5 – SPI Slave Functional name External pin name SSPIDO: Output from serial shift register (MISO) GP6 SSPIDI: Input to s

DS4830 User’s Guide 108 12.5.4 – SPI Slave Register Descriptions SPI Slave Module has four SFR registers. These are SPICN_S, SPICF_S,

DS4830 User’s Guide 109 12.5.4.2 – SPI Configuration Register (SPICF_S) SPICF_S Register Address: M1 [13h] Bit 7 6 5 4 3 2 1 0 Name ESPII SAS - -

DS4830 User’s Guide 11 SECTION 2 – ARCHITECTURE The DS4830 contains a MAXQ20 low-cost, high-performance, CMOS, fully static microcontroller with fl

DS4830 User’s Guide 110 SECTION 13 – 3-WIRE The DS4830 has proprietary 3-Wire master interface for communication with MAXIM 3-wire laser drivers (

DS4830 User’s Guide 111 13.1.1.1 – Write Mode (RWN=0) The 3-Wire master generates 16 clock cycles on MCL pin. It outputs 16-bits (MSB first DADDR d

DS4830 User’s Guide 112 13.2 – 3-Wire Register Descriptions The 3-Wire interface is controlled by two SFR registers. These are the 3-

DS4830 User’s Guide 113 SECTION 14 – PWM The DS4830 provides ten independent PWM output pins that can be used to create DC-DC power supply contro

DS4830 User’s Guide 114 PWMCN.REG_SEL = 00bPWMCN.PWM_SEL =n PWMCN.REG_SEL = 01bPWMCN.PWM_SEL =n PWMCN.REG_SEL = 1xbPWMCN.PWM_SEL =n DCYC0 (Ch0)DCYC

DS4830 User’s Guide 115 14.2 – Individual PWM Channel Operation Figure 14-3: Block diagram of one PWM channel. The DS4830 has 10 PWMs whic

DS4830 User’s Guide 116 PWM Output High Time128 CyclesPWM Output Low Time384 CyclesPWM Frame = 512 Cycles9-bit PWM Operation in Normal ModeDCYCn

DS4830 User’s Guide 117 PWM Output High Time32 CyclesPWM Output Low Time96 CyclesPWM Frame = 512 Cycles9 bit PWM Operation in 4 Slot pulse spreadin

DS4830 User’s Guide 118 Table 14-2. Slot frequencies for various resolution with different PWM Clocks Resolution No of Slots Clock (MHz) Frame f

DS4830 User’s Guide 119 14.2.4 – Alternate PWM Output Table 14-3 shows the mapping of each PWM Output. The PWM outputs PW0 to PW7 are also multip

DS4830 User’s Guide 12 prefix register is cleared to zero after one cycle so it will not affect any other instructions. The write to the prefix re

DS4830 User’s Guide 120 14.2.3.1 – PWM DELAY with PWMSYNC SFR The PWM channels to be synchronized must have the same configurations (Resolution,

DS4830 User’s Guide 121 PWM_SEL REG_SEL Local Register Selected 0 0 Duty Cycle Register PWM Channel 0 (DCYC0) 0 1 PWM Configuration Register PWM Ch

DS4830 User’s Guide 122 14.3.2.1 – Local Register DCYCn PWMCN REG_SEL = 00b PWMDATA[15:0]  DCYCn[15:0] BIT NAME DESCRIPTION 15:12 Reserved Reserv

DS4830 User’s Guide 123 14.3.2.2 – Local Register PWMCGFn Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INV - ALT_ LOC PWMEN - CLK_SEL PS32 - PS4 - RE

DS4830 User’s Guide 124 14.3.2.3 – Local Register PWMDLYn PWMCN REG_SEL = 1xb PWMDATA[15:0]  PWMDLY[15:0] BIT NAME DESCRIPTION 15:12 Reserved Rese

DS4830 User’s Guide 125 14.4 – PWM Output Code Examples 14.4.1 – 9-bit PWM Output in normal mode with core clock Creating a 25% duty cycle with 2

DS4830 User’s Guide 126 SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS 15.1 – Overview The DS4830 provides general-purpose input/output (GP

DS4830 User’s Guide 127 Table 15-1. GPIO Pins and Multiplexed Functions Port Index Pin Name Pin No. Default Function Special Function-1 Special f

DS4830 User’s Guide 128 Table 15-2. GPIO Registers Register Function Port 0 Port 1 Port 2 Port 6 POp Port Output Register M0[02h

DS4830 User’s Guide 129 15.2 – GPIO Port 0 Register Descriptions Port 0 provides eight GPIO pins that are multiplexed with ADC, DAC, Sample and Hol

DS4830 User’s Guide 13 Table 2-1. Register-to-Register Transfer Operations SOURCE REGISTER SIZE (BITS) DESTINATION REGISTER SIZE (BITS) PREFIX SET?

DS4830 User’s Guide 130 15.2.5 – GPIO Port 0 External Interrupt Flag Register (EIF0) Bit # 7 6 5 4 3 2 1 0 Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 Res

DS4830 User’s Guide 131 15.3.3 – GPIO Input Register for Port 1 (PI1) Bit # 7 6 5 4 3 2 1 0 Name PI1_7 PI1_6 PI1_5 PI1_4 PI1_3 PI1_2 PI1_1 PI1_0

DS4830 User’s Guide 132 PD2 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins.

DS4830 User’s Guide 133 15.5 – GPIO Port 6 Register Descriptions Port 6 provides seven GPIO pins that are multiplexed with the test access port (T

DS4830 User’s Guide 134 15.5.5 – GPIO Port 6 External Interrupt Flag Register (EIF6) Bit # 7 6 5 4 3 2 1 0 Name Reserved IE6 IE5 IE4 IE3 IE2 IE1

DS4830 User’s Guide 135 SECTION 16 – GENERAL-PURPOSE TIMERS The DS4830 has two identical 16-bit general-purpose timers. Each timer has the followin

DS4830 User’s Guide 136 In compare mode, the timer module begins counting from 0x0000 and when the value in the GTV register matches the value in t

DS4830 User’s Guide 137 16.2 – Timer Register Descriptions Each General Timer module has three independent SFR registers. These are GTCN, GTV and

DS4830 User’s Guide 138 16.2.2 – General Timer Value Register (GTV) GTV1 Register Address: M0 [06h] GTV2 Register Address: M3 [06h] Bit 15 14 13 1

DS4830 User’s Guide 139 SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM) The DS4830 provides features to allow monitoring its power supply. The Supply Vol

DS4830 User’s Guide 14 The width of the stack is 16 bits to accommodate the instruction pointer size. On reset, the stack pointer SP initializes to

DS4830 User’s Guide 140 SECTION 18 – HARDWARE MULTIPLIER MODULE The hardware multiplier module can be used by the DS4830 to support hig

DS4830 User’s Guide 141 18.3 – Register Output Selection The Hardware Multiplier implements the MC Register Write Select (MCW) control bit so that

DS4830 User’s Guide 142 The specified hardware multiplier operation begins when the final operand(s) is loaded and will complete in a single cycle.

DS4830 User’s Guide 143 18.5.1 – Multiplier Control Register (MCNT) Bit 7 6 5 4 3 2 1 0 Name OF MCW CLD SQU OPCS MSUB MMAC SUS Reset 0 0 0 0 0 0 0

DS4830 User’s Guide 144 18.5.2 – Multiplier Operand A Register (MA) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name MA.15 MA.14 MA.13 MA.12 MA.11 MA

DS4830 User’s Guide 145 18.6 – Hardware Multiplier Examples The following are code examples of multiplier operations. ;Unsigned Multiply 16-bit x

DS4830 User’s Guide 146 SECTION 19 – WATCHDOG TIMER 19.1 - Overview The Watchdog Timer is a user programmable clock counter that can serve as a tim

DS4830 User’s Guide 147 Table 19-1. Watchdog Operating States EWT EWDI WDIF Actions x X 0 No interrupt has occurred. 0 0 x Watchdog disable, clock

DS4830 User’s Guide 148 BIT NAME DESCRIPTION 7 POR Power-On Reset Flag: This bit is set to 1 whenever a power-on/brownout reset occurs. It is una

DS4830 User’s Guide 149 SECTION 20 – TEST ACCESS PORT (TAP) The DS4830 incorporates a Test Access Port (TAP) and TAP controller for communication w

DS4830 User’s Guide 15 2.4.2 – Program Memory Mapping The DS4830’s mapping of the three memory segments (flash, SRAM, and utility ROM) as program m

DS4830 User’s Guide 150 20.1 – TAP Controller The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK signa

DS4830 User’s Guide 151 20.2 – TAP State Control The TAP provides an independent serial channel to communicate synchronously with the host syste

DS4830 User’s Guide 152 Table 20-3 - Instruction Register (IR2:0) Encodings IR2:0 Instruction Function Serial Data Shift Register Selection

DS4830 User’s Guide 153 For the host to establish a specific data communication link, a private instruction must be loaded into the IR2:0 register.

DS4830 User’s Guide 154 Figure 20-4: TAP Controller Debug Mode DR-Scan Example Run-Test/IdleSelect-DR-ScanCapture-DRShift-DRExit1-DRP

DS4830 User’s Guide 155 SECTION 21 – IN-CIRCUIT DEBUG MODE The DS4830 is equipped with embedded debug hardware and embedded ROM firmware developed

DS4830 User’s Guide 156 TDI TDO9090X X s1 s0Host Command / Data Input StatusDS4830DS4830 Data Output Figure 21-2: 10-Bit Word Format Table 21-1: S

DS4830 User’s Guide 157 Table 21-2. Background Mode Commands Opcode Command Operation 0000-0000 No Operation No operation. (Default state for Debug

DS4830 User’s Guide 158 21.1.1.1 – Breakpoint 0 Register (BP0) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BP0.15 BP0.14 BP0.13 BP0.12 BP0.11 BP

DS4830 User’s Guide 159 When REGE = 1: This register serves as one of the two register breakpoints. A break occurs when the destination register ad

DS4830 User’s Guide 16 pointer. If the data pointer is used as destination, the core performs a store operation that writes data to the memory loc

DS4830 User’s Guide 160 21.2 – Debug Mode There are two ways to enter the Debug Mode from Background Mode: 1. Issuance of the Debug command direc

DS4830 User’s Guide 161 (e.g., Unlock Password) require additional data from the host. Some commands need only to provide an indication of comp

DS4830 User’s Guide 162 Op Code Command Operation 0010-0101 Write data memory Write data to a selected data memory location. This command requires

DS4830 User’s Guide 163 Table 21-4. Output from Read Register Map Command WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER W

DS4830 User’s Guide 164 debug engine. Also, note that the interrupt handler is an essential part of the CPU and a pending interru

DS4830 User’s Guide 165 21.3 – In-Circuit Debug Peripheral Registers The following peripheral registers are used to control the in-circuit debug m

DS4830 User’s Guide 166 21.3.3 – In-Circuit Debug Control Register (ICDC, M2[1Ah]) Bit 7 6 5 4 3 2 1 0 Name DME - REGE - CMD3 CMD2 CMD1 CMD0 Res

DS4830 User’s Guide 167 21.3.4 – In-Circuit Debug Flag Register (ICDF, M2[1Bh]) Bit 7 6 5 4 3 2 1 0 Name - - - - PSS1 PSS0 JTAG_SPE TXC Reset 0 0

DS4830 User’s Guide 168 21.3.7 – In-Circuit Debug Data Register (ICDD, M2[1Eh]) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ICDD.15 ICDD.14 IC

DS4830 User’s Guide 169 SECTION 22 – IN-SYSTEM PROGRAMMING The DS4830 contains an internal bootstrap loader utilizing the JTAG or I2C interfaces.

DS4830 User’s Guide 17 2.4.4.1 – Memory Map When Executing from Flash Memory When executing from the flash memory:  Read and write operations of

DS4830 User’s Guide 170 If none of the preceding conditions have been met, the DS4830 ROM code will be complete. The DS4830 will then jump to prog

DS4830 User’s Guide 171 Table 22-2 JTAG Bootloader Status Bits Bits 1:0 Status Condition 00 Reserved Invalid condition. 01 Reserved Invalid condit

DS4830 User’s Guide 172 22.2.1 – JTAG Bootloader Protocol The JTAG port consists of a shift register. As data is clocked into TDI, data will be c

DS4830 User’s Guide 173 22.3 – Bootloader Commands Commands for the DS4830 loader are grouped into families. All bootloader commands begin with

DS4830 User’s Guide 174 22.3.4 - Command 03h – Password Match Byte 1 Bytes 2 to 33 Byte 34 Byte 35 Command Data In NOP Return Input 03h 32-Byte

DS4830 User’s Guide 175 22.3.6 - Command 05h – Get Supported Commands Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Command NOP Data Out Data

DS4830 User’s Guide 176 22.3.11 - Command 10h – Load Code Byte 1 Byte 2 Byte 3 Byte 4 (Length) Bytes Byte Length+5 Byte Length+6 Command Data I

DS4830 User’s Guide 177 22.3.14 - Command 21h – Dump Data Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 5 Byte 6 Length Bytes Byte Length+7 Command D

DS4830 User’s Guide 178 This command operates in the same manner as the Load Data command, except that instead of writing the input data into SRAM,

DS4830 User’s Guide 179 SECTION 23 – PROGRAMMING The following section provides a programming overview of the DS4830. For full details on the inst

DS4830 User’s Guide 18 2.4.4.2 – Memory Map When Executing from Utility ROM When executing from the utility ROM:  Read and write operations of SR

DS4830 User’s Guide 180 23.3.1 – Loading an 8-bit register with an immediate value Any writeable 8-bit register with a sub-index from 0h to 7h wit

DS4830 User’s Guide 181 16-bit destination  concatenation(8-bit source, 8-bit source) Two 8-bit source registers can be concatenated and stored in

DS4830 User’s Guide 182 As with other instructions, prefixing is required to select destination registers beyond index 07h. The MOVE instruction

DS4830 User’s Guide 183  MOVE Acc, Acc (Recirculation of active accumulator contents)  XCHN (Exchange nibbles within each byte of active

DS4830 User’s Guide 184 23.5.3 – ALU operations using the active accumulator and a source The following arithmetic and logical operations can use a

DS4830 User’s Guide 185 Since the Sign flag is a dynamic reflection of the high bit of the active accumulator, any instruction that changes the val

DS4830 User’s Guide 186  MOVE Acc.<b>, C (Set selected active accumulator bit to Carry)  AND Acc.<b> (Carry = Carry AND sel

DS4830 User’s Guide 187 23.7.3 - Conditional jumps Conditional jumps transfer program execution based on the value of one of the status flags (C,

DS4830 User’s Guide 188 move LC[1], #10h ; loop 16 times ... LoopTop: ; loop address not relative to djnz

DS4830 User’s Guide 189 To support high priority interrupts while servicing another interrupt source, the IMR register may be used to create a user

DS4830 User’s Guide 19 2.4.4.3 – Memory Map When Executing from SRAM When executing from the SRAM:  The utility ROM can be read as data, starting

DS4830 User’s Guide 190 add @SP-- ; sum the last three words pushed onto the stack add @SP-- ; with Acc, disregarding ove

DS4830 User’s Guide 191 bit that is utilized only for word mode data pointer access). Switching from byte to word access mode or vice versa does no

DS4830 User’s Guide 192 SECTION 24 – INSTRUCTION SET Table 24-1. Instruction Set Summary Mnemonic Description 16-bit Instruction Word Status Bits

DS4830 User’s Guide 193 Note 2: Only module 8 and modules 0-5 are supported by these single-cycle bit operations. Potentially affects C or E if PSF

DS4830 User’s Guide 194 AND src Logical AND Description: Performs a logical-AND between the act

DS4830 User’s Guide 195 {L/S}CALL src {Long/Short} Call to subroutine Description: Perform

DS4830 User’s Guide 196 CMP src Compare Accumulator Description: Compare for equality between the active accumula

DS4830 User’s Guide 197 {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Descript

DS4830 User’s Guide 198 {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs a

DS4830 User’s Guide 199 {L/S} JUMP C / {L/S} JUMP NC, src Conditional {Long/Short} Jump o

DS4830 User’s Guide 2 Contents SECTION 1 – OVERVIEW ...

DS4830 User’s Guide 20 2.5 – Data Alignment To support merged program and data memory operation while maintaining efficient memory space usage, the

DS4830 User’s Guide 200 JUMP NZ Operation: Z=0: IP  IP + src (relative) –or— src (absolute) Z=1: IP  IP + 1 Encoding: 15

DS4830 User’s Guide 201 MOVE dst, src Move Data Description: Moves data from a sp

DS4830 User’s Guide 202 MOVE dst, src (continued) Destination Specifier Codesdst dst Bit Encodin

DS4830 User’s Guide 203 Example(s): MOVE A[0], A[3] ; A[0]  A[3] MOVE DP[0], #110h ; DP[0]  #0110h (PFX[0] re

DS4830 User’s Guide 204 MOVE C, Acc.<b> Move Accumulator bit to Carry Flag Description: Replaces the Carry (C) status flag with

DS4830 User’s Guide 205 MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Statu

DS4830 User’s Guide 206 NEG Negate Accumulator Description: Performs a negation (two’s comple

DS4830 User’s Guide 207 POP dst Pop Word from the Stack Description: Pops a single word from the stack (@SP) to the spe

DS4830 User’s Guide 208 Operation: SP  ++SP Encoding: 15 0 f000 1101 ssss ssss Example(s): PUSH GR ; GR=0F3Fh

DS4830 User’s Guide 209 RET C / RET NC Conditional Return on Status Flag RET Z / RET NZ RET S Desc

DS4830 User’s Guide 21 BROWNOUT STATECPU DISABLEDANALOG ACTIVESYSTEM CLOCKSTARTUP DELAY CPU MODEDIGITAL CORE ONANALOG ONCODE EXECUTIONVDD > VBOV

DS4830 User’s Guide 210 RETI Return from Interrupt Description: RETI pops a single word from

DS4830 User’s Guide 211 RETI Z Operation: Z=1: IP  @SP-- INS 0 Z=0: IP  IP + 1 Encoding: 15

DS4830 User’s Guide 212 RL / RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accu

DS4830 User’s Guide 213 RR / RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accu

DS4830 User’s Guide 214 SLA / SLA2 / SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the a

DS4830 User’s Guide 215 SR Shift Accumulator Right SRA / SRA2 / SRA4

DS4830 User’s Guide 216 SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry Flag Acc.[13:0] Acc

DS4830 User’s Guide 217 SUB / SUBB src Subtract / Subtract with Borrow Description: Subtracts the specifie

DS4830 User’s Guide 218 XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumu

DS4830 User’s Guide 219 XOR src Logical XOR Description: Performs a logical-XOR between the

DS4830 User’s Guide 22 2.6.4 – Internal System Resets There are two possible sources of internal system resets. An internal reset will hold the D

DS4830 User’s Guide 220 SECTION 25 – UTILITY ROM 25.1 – Overview The DS4830 utility ROM includes routines that provide the following functions to

DS4830 User’s Guide 221 25.2 – In-Application Programming Functions 25.2.1 – UROM_flashWrite Function UROM_flashWrite Summary Programs a single w

DS4830 User’s Guide 222 25.3 – Data Transfer Functions The DS4830 cannot access data from the same memory segment that is currently

DS4830 User’s Guide 223 25.3.1 – UROM_moveDP0 Function UROM_moveDP0 Summary Reads the byte/word value pointed to by DP[0]. Inputs DP[0]: Address to

DS4830 User’s Guide 224 25.3.4 – UROM_moveDP1 Function UROM_moveDP1 Summary Reads the byte/word value pointed to by DP[1]. Inputs DP[1]: Address to

DS4830 User’s Guide 225 25.3.7 – UROM_moveBP Function UROM_moveBP Summary Reads the byte/word value pointed to by BP[OFFS]. Inputs BP[OFFS]: Addres

DS4830 User’s Guide 226 25.3.10 – UROM_copyBuffer Function UROM_copyBuffer Summary LC[0] bytes/words (up to 256) from DP[0] to BP[OFFS]. Inputs DP[

DS4830 User’s Guide 227 25.4 – Utility ROM Examples 25.4.1 – Reading Constant Word Data from Flash UROM_moveDP0inc equ 08483h move DPC, #1Ch

DS4830 User’s Guide 23 SECTION 3 – SYSTEM REGISTER DESCRIPTIONS Most functions of the DS4830 are controlled by sets of registers. These registers p

DS4830 User’s Guide 24 Table 3-2. System Register Bit Functions REGISTER REGISTER BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AP — — —

DS4830 User’s Guide 25 3.1 Accumulator Pointer Register (AP, 8h[0h]) Initialization: This register is cleared to 00h on all forms of reset. Acce

DS4830 User’s Guide 26 3.5 Interrupt Mask Register (IMR, 8h[6h]) Initialization: This register is cleared to 00h on all forms of reset. Access:

DS4830 User’s Guide 27 3.8 Watchdog Control Register (WDCN, 8h[Fh]) Initialization: Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; fo

DS4830 User’s Guide 28 3.10 Prefix Register (PFX[n], Bh[n]) Initialization: This register is cleared to 0000h on all forms of reset. Access: Unr

DS4830 User’s Guide 29 3.16 Frame Pointer Offset Register (OFFS, Eh[3h]) Initialization: This register is cleared to 00h on all forms of reset.

DS4830 User’s Guide 3 7.1.3 – Temperature Conversion ...

DS4830 User’s Guide 30 3.22 General Register High Byte (GRH, Eh[9h]) Initialization: This register is cleared to 00h on all forms of reset. Acce

DS4830 User’s Guide 31 SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS Reg M0 M1 M2 M3 M4 M5 0 PO2 I2CBUF-M I2CBUF-S MCNT DACD0 QTDATA 1 PO1 I2CST-M I

DS4830 User’s Guide 32 MODULE 0 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PO2 00h PO2[7:0] PO1 01h PO1[7

DS4830 User’s Guide 33 MODULE 1 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CBUF_M 00h - D[7:0] I2CST_M 01h I2CBUS I2CBUSY - - I2CSPI I

DS4830 User’s Guide 34 MODULE 2 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CBUF_S 00h - D[7:0] I2CST_S 01h I2CBUS I2CBUSY - - I2CSPI I

DS4830 User’s Guide 35 MODULE 3 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCNT 00h OF MCW CLD SQU OPCS MSUB MMAC SUS MA

DS4830 User’s Guide 36 SECTION 5 – INTERRUPTS The DS4830 provides a single, programmable interrupt vector (IV) that can be used to ha

DS4830 User’s Guide 37 Note: Some of the DS4830 module and peripheral interrupts sources are shown in the Figure 5-1 interrupt hier

DS4830 User’s Guide 38 I2C Slave Transmit Complete Interrupt I2CST_S.I2CTXI I2CIE_S.I2CTXIE I2C Slave Receive Ready Interrupt I2CST_S. I2CRXI I2CIE

DS4830 User’s Guide 39 pending interrupt. The peripheral register bits inside the module also provide a way to differentiate among

DS4830 User’s Guide 4 11.1 – Detailed Description ...

DS4830 User’s Guide 40 5.3 – Interrupt System Operation The interrupt handler hardware responds to any interrupt event when it is enabled. An inte

DS4830 User’s Guide 41 When the prefix register is activated by writing a value to it, it retains that value only for the next clock cycle. For the

DS4830 User’s Guide 42 SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) The DS4830 contains eight 12-bit digital-to-analog converters (DACs). Each DA

DS4830 User’s Guide 43 The DAC Data register programs the DAC for a particular voltage output depending on the value of this register and the refer

DS4830 User’s Guide 44 6.2.1 – DAC Configuration Register (DACCFG) Register Address: M4 [08h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DAC

DS4830 User’s Guide 45 6.3 – DAC Code Examples 6.3.1 – DAC0 enabled with internal reference and output voltage is configured for 50%

DS4830 User’s Guide 46 SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) The DS4830 provides a 13-bit analog-to-digital converter (ADC) with 26-input

DS4830 User’s Guide 47 By default, the external channels GP0-15 are general-purpose input. The DS4830 has the Pin Select Register (PINSEL). The PI

DS4830 User’s Guide 48 case for sequence conversion, where the starting and ending configuration address is the same. The configurat

DS4830 User’s Guide 49 3. S/H0 has priority over S/H1 if both S/Hs are ready for conversion. However, in next slot for S/H, the S/H1 will get slot

DS4830 User’s Guide 5 14.2.3 – Pulse Spreading...

DS4830 User’s Guide 50 ADACQ[3:0]. Table 7-2 shows the extended acquisition time in terms of core clocks at different ADACQ[3:0] The total acquisi

DS4830 User’s Guide 51 location configured in the ALT_LOC[4:0] bits in the ADDATA during ADC configuration (ADST.ADCFG = 1). This buffer is accesse

DS4830 User’s Guide 52 7.2 – ADC Register Descriptions The ADC is controlled by ADC SFR registers. The PINSEL register is used to configure pins as

DS4830 User’s Guide 53 7.2.2 – ADC Status Register (ADST) Register Address: M2[06h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - SH1DAI SH0

DS4830 User’s Guide 54 7.2.3 – PIN Select Register (PINSEL) Register Address: M2 [12h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PINSEL.15 PIN

DS4830 User’s Guide 55 6 ADALIGN ADC Data Alignment Select. This bit selects the ADC data alignment mode. Setting this bit to ‘1’ returns ADC data

DS4830 User’s Guide 56 7.2.6 – Temperature Control Register (TEMPCN) Register Address: M2 [0Bh] The Temperature Control register TEMPCN config

DS4830 User’s Guide 57 7.2.8 – ADC External Temperature Offset Register (TOEX) Register Address: M1 [1Ah] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS4830 User’s Guide 58 7.3 – ADC Code Examples 7.3.1 – One Sequence of 4 Voltage Conversions for Ch0 (Diff), Ch1 (Diff), Ch14 (Single) and Ch15 (Si

DS4830 User’s Guide 59 while (1) { while (!ADST_bit.ADDAI); //wait for conversions to complete ADST_bit.ADDAI = 0; ADST_bit.AD

DS4830 User’s Guide 6 SECTION 18 – HARDWARE MULTIPLIER MODULE ...

DS4830 User’s Guide 60 SECTION 8 – SAMPLE AND HOLD The DS4830 has two independent, but identical, Sample and Hold differential channels. Sample an

DS4830 User’s Guide 61 Sample Time (min 300nSec)Conversion Time Depends upon ADC SequencingSample and Hold Sample and Conversion TimingsSample Puls

DS4830 User’s Guide 62 circuit. When the clock select bit CLK_SEL is set to ‘1’, the external clock (CLKIN on the DACPW2 pin) is used for the samp

DS4830 User’s Guide 63 SHEN0/1 orINT_REIG0/1Sample PulseSample Pulse Width with external clockCLKIN ….Falling edge (Sample stop) depends upon SSC[3

DS4830 User’s Guide 64 8.1.5 – Sample and Hold Data Reading Each sample and hold has defined data buffer locations where the ADC controller writes

DS4830 User’s Guide 65 8.2 – Sample and Hold Register Descriptions The sample and hold has two SFRs. These are Sample and Hold Control Register (SH

DS4830 User’s Guide 66 125s. During fast mode, the sample and hold conversion priority is increased over voltage channels in the sequence and the

DS4830 User’s Guide 67 8.2.2 – Sample and Hold Internal Trigger Enable Register (SENR) SENR Register Address: M2[05h] Bit 15 14 13 12 11 10 9 8

DS4830 User’s Guide 68 SECTION 9 – QUICK TRIP (FAST COMPARATOR) The DS4830 has 16 8-bit quick trips with 16-input Analog MUX (Figure 9-1). The MUX

DS4830 User’s Guide 69 By default, the external channels GP0-15 are general-purpose input. The DS4830 has the Pin Select Register (PINSEL). The PIN

DS4830 User’s Guide 7 22.2.1 – JTAG Bootloader Protocol ...

DS4830 User’s Guide 70 (channel 7 + differential mode) and 06h (channel 6 + single-ended). See below Table 9-2 for the quick trip

DS4830 User’s Guide 71 Channel 5LT HTChannel 6LT HTChannel 7LT HT……….Channel 5LT HTChannel 6LT HTChannel 7LT HT……….Channel 6*LT HTChannel 6*LT HT*

DS4830 User’s Guide 72 9.2 – Quick Trip Register Descriptions The quick trip has 7 SFRs. These are the Quick Trip Control Register (QTCN), Quick Tr

DS4830 User’s Guide 73 QTDATA Register map when RW_LST = 0 (in the QTCN Register) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - LOW or HIGH THRE

DS4830 User’s Guide 74 9.2.3 – Low Trip Interrupt Register (LTI) LTI Register Address: M5 [02h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IF[1

DS4830 User’s Guide 75 9.2.7 – Quick Trip List Register (QTLST) QTLIST Register Address: M5 [0Ah] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name

DS4830 User’s Guide 76 SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE The DS4830 provides an I2C-compatible master controller that allows the DS4830

DS4830 User’s Guide 77 Figure 10-1: I2C Clock Generation The master I2C controller’s ability to monitor the state of SCL allows the master to o

DS4830 User’s Guide 78  Whenever SCL goes low. If the SCL line is low for a period longer than specified in the timeout register, the I2C contro

DS4830 User’s Guide 79 Figure 10-3: Master I2C Generated START and STOP 10.1.6 – Generating a STOP To end an I2C transfer, a STOP must be trans

DS4830 User’s Guide 8 23.6.2 - Zero Flag ...

DS4830 User’s Guide 80 10.1.7 – Transmitting a Slave Address The first byte after an I2C start or restart condition is the slave address byte. Thi

DS4830 User’s Guide 81 I2CNACKI = ACKNOWLEDGETransmit I2CBUF_M[7:0] I2CBUF_M[0] I2CMODEI2CBUSY=1I2CTXI=1I2CBUSY=0Write to I2CBUF_MRECEIVEAC

DS4830 User’s Guide 82 1. If I2CBUF_M is empty, the I2C master controller will copy the data from the shift register into I2CBUF_M. The I2CRXI fl

DS4830 User’s Guide 83 10.1.10 – I2C Master Clock Stretching The Master I2C Controller is capable of clock stretching at the end of each transfer c

DS4830 User’s Guide 84 10.1.12 – Operation as a Slave The DS4830 contains two I2C interfaces, the master (MSDA and MSCL) and slave (DS4830 SDA and

DS4830 User’s Guide 85 10.2 – I2C Master Controller Register Description Following are the registers that are used to control the I2C Master Inter

DS4830 User’s Guide 86 10.2.2 – I2C Master Status Register (I2CST_M) Address: M1[01h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CBUS I2CBUSY

DS4830 User’s Guide 87 10.2.3 – I2C Master Interrupt Enable Register (I2CIE_M) Address: M1[02h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - -

DS4830 User’s Guide 88 10.2.5 – I2C Master Clock Control Register (I2CCK_M) Address: M1[0Dh] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CCKH7

DS4830 User’s Guide 89 SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE The DS4830 provides an I2C-compatible slave controller that allows the DS4830 to

DS4830 User’s Guide 9 SECTION 1 – OVERVIEW The DS4830 System Management Microcontroller provides a complete optical control, calibration, and monit

DS4830 User’s Guide 90 11.1 – Detailed Description 11.1.1 – Default Operation The I2C slave controller is enabled (I2CCN_S.I2CEN=1) by default. A

DS4830 User’s Guide 91 TransmittingByteReceiving ByteYReceiveAddr[6:0] + R/WMatchI2CSLA_S[7:1]?TransmitI2CACKI2CBUSY=0NI2CAMI=1Set I2CMODEAccording

DS4830 User’s Guide 92 Following the 8th data (least significant bit) being shifted to SDA, the SDA line will be released by the

DS4830 User’s Guide 93 11.1.8 – Clock Stretching If a slave device cannot receive or transmit another complete byte of data, it may hold SCL low, f

DS4830 User’s Guide 94 1. The I2C slave controller is in the idle state and there is no communications on the I2C bus. The timer should not generat

DS4830 User’s Guide 95 11.2 – I2C Slave Controller Register Description Following are the registers that are used to control the I2C Sla

DS4830 User’s Guide 96 11.2.2 – I2C Slave Status Register (I2CST_S) Address: M2[01h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CBUS I2CBUSY

DS4830 User’s Guide 97 11.2.3 – I2C Slave Interrupt Enable Register (I2CIE_S) Address: M2[02h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - -

DS4830 User’s Guide 98 11.2.5 – I2C Slave Data Buffer Register (I2CBUF_S) Address: M2[00h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - -

DS4830 User’s Guide 99 SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI) The DS4830 provides two independent Serial Peripheral Interfaces (SPI) – one