Maxim-integrated DS4830 Optical Microcontroller Manuel d'utilisateur télécharger pdf (Page 100)

DS4830 User’s Guide

100

edge is used to sample the serial shift data. The Clock Phase Select (CKPHA; SPICF.1) bit controls whether the active or

inactive clock edge is used to latch the data. When CKPHA is set to 1, data is sampled on the inactive clock edge (clock

returning to the idle state). When CKPHA is set to 0, data is sampled on the active clock edge (clock transition to the

active state). Together, the CKPOL and CKPHA bits allow four possible SPI data transfer formats illustrated in Figure 12-2

and Figure 12-3. The Slave Select signal can remain asserted between successive transfers. Table 12-1 illustrates the

SPI modes.

Table 12-1 SPI Modes

CKPOL

CKPHA

Mode

Sample Point

Mode 0

Rising edge

Mode 1

Falling edge

Mode 2

Falling edge

Mode 3

Rising edge

CKPO L=0

CKPH A=1

CKPO L=1

CKPH A=1

M OSI/M ISO

SSEL

SAS=1

Sam pling Points

Transfer Cycle

LSBM SB

1 2 3 4 5 6 7 8

Figure 12-2: SPI Transfer Formats (CKPHA=1)

CKPOL=0

CKPHA=0

CKPOL=1

CKPHA=0

MOSI/MISO

SSEL

SAS=1

Sampling Points

Transfer Cycle

LSBMSB

1 2 3 4 5 6 7 8

MSB

MSB of

Transfer

Figure 12-3: SPI Transfer Formats (CKPHA=0)

1 2 ... 95 96 97 98 99 100 101 102 103 104 105 ... 226 227

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Maxim-integrated DS4830 Optical Microcontroller Manuel d'utilisateur Page 100

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