
DS4830 User’s Guide
88
10.2.5 – I
2
C Master Clock Control Register (I2CCK_M)
Address: M1[0Dh]
I
2
C Clock High Period. These bits define the high period of the I
2
C clock. This period
is defined by the number of system clocks. The high time duration is calculated using the
following equation:
I
2
C High Time Period = System Clock Period x (I2CCKH[7:0] + 1)
I2CCKH[7:0] must be set to a minimum value of 2 to ensure proper operation. Any value
less than 2 will be set to 2.
I
2
C Clock Low Period. These bits define the low period of the I
2
C clock. This period is
defined by the number of system clocks. The low time duration is calculated using the
following equation:
I
2
C Low Time Period = System Clock Period x (I2CCKL[7:0] + 1)
I2CCKL[7:0] must be set to a minimum value of 4 to ensure proper operation. Any value
less than 4 will be set to 4.
10.2.6 – I
2
C Master Timeout Register (I2CTO_M)
Address: M1[0Eh]
The I2CTO_M register determines the length of the timeout interval. The timeout interval is defined by the number of I
2
C bit periods
(SCL high + SCL low). When cleared to 00h, the timeout function is disabled. When set to any other value, the I
2
C controller waits until
the timeout expires and sets the I2CTOI flag. The timeout period is:
I
2
C Timeout = I
2
C Bit Rate x (I2CTO[7:0] + 1)
The timeout timer resets to 0 and starts to count after each of the following events.
The I2CSTART bit is set.
The I2CSTOP bit is set.
Any time that SCL goes low.
10.2.7 – I
2
C Master Address Register (I2CSLA_M)
Address: M1[0Fh]
This register has no function when operating in master mode.
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