Maxim-integrated DS4830 Optical Microcontroller Manuel d'utilisateur Page 132
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DS4830 User’s Guide
132
PD2 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is
independently controlled by its direction bit. When PD2.n (n = 0 to 7) is set to 1, the pin is an output; data in the PO2.n bit
will be driven on the pin. When PD2.n is cleared to 0, the pin is an input, and allows an external signal to drive the pin.
Note that each port pin has a weak pull-up circuit when functioning as an input. The P channel pull-up transistor is
controlled by the PO2.n bit. If PO2.n is set to 1, the corresponding weak pull-up is turned on, if the PO2.n bit is cleared to
0, the weak pull-up is turned off and the pin’s input is high-impedance. The weak pull-up transistor is not available on pins
P2.6 and P2.7.
15.4.2 – GPIO Output Register Port 2 (PO2)
Bit #
7
6
5
4
3
2
1
0
Name
PO2_7
PO2_6
PO2_5
PO2_4
PO2_3
PO2_2
PO2_1
PO2_0
Reset
1
1
1
1
1
1
1
1
Access
rw
rw
rw
rw
rw
rw
rw
rw
PO2 is an 8-bit register that controls the output data of a GPIO pin. If the pin is setup to be an output (PD2.n = 1), the
data in PO2.n will be output on the pin. If the pin is set as an input (PD2.n = 0), setting PO2.n to a 1 enables a p-channel
weak pull-up, otherwise the pin’s input is high impedance.
15.4.3 – GPIO Input Register for Port 2 (PI2)
Bit #
7
6
5
4
3
2
1
0
Name
PI2_7
PI2_6
PI2_5
PI2_4
PI2_3
PI2_2
PI2_1
PI2_0
Reset
s
s
s
s
s
s
s
s
Access
r
r
r
r
r
r
r
r
PI2 is an 8-bit register which contains the data that is applied to the GPIO pins. The PI2 input register contains valid input
data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states
applied to the pins.
15.4.4 – GPIO Port 2 External Interrupt Edge Select Register (EIES2)
Bit #
7
6
5
4
3
2
1
0
Name
IT7
IT6
IT5
IT4
IT3
IT2
IT1
IT0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
The EIES2 register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge. Setting the
IESP2_n bits to 0 will trigger the corresponding interrupt on a positive edge. When these bits are set to a 1, the interrupt
will be on a negative edge.
15.4.5 – GPIO Port 2 External Interrupt Flag Register (EIF2)
Bit #
7
6
5
4
3
2
1
0
Name
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
These bits are set when a negative edge (IESP2.n = 1) or a positive edge (IESP1.n = 0) is detected on the P2.n pin.
Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits will
remain set until cleared by software or a reset. These bits must be cleared by software before exiting the interrupt service
routine or another interrupt will be generated as long as the bit remains set.
15.4.6 – GPIO Port 2 External Interrupt Enable Register (EIE2)
Bit #
7
6
5
4
3
2
1
0
Name
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
Setting any of these bits to 1 will enable the corresponding external interrupt. Clearing any of the bits to 0 will disable the
corresponding interrupt function.
- OpticalMicrocontroller 1
- User’sGuide 1
- Contents 2
- SECTION 1 – OVERVIEW 9
- DS4830 User’s Guide 10
- SECTION 2 – ARCHITECTURE 11
- 2.2 – Register Space 12
- 2.3 – Memory Types 13
- 2.5 – Data Alignment 20
- 2.6 – Reset Conditions 20
- 2.7 – Clock Generation 22
- SECTION 5 – INTERRUPTS 36
- 5.1 – Servicing Interrupts 37
- 6.1 – Detailed Description 42
- 6.3 – DAC Code Examples 45
- 7.1 – Detailed Description 46
- 7.3 – ADC Code Examples 58
- SECTION 8 – SAMPLE AND HOLD 60
- 9.1 – Detailed Description 68
- SECTION 10 – I 76
- SECTION 11 – I 89
- C-COMPATIBLE SLAVE INTERFACE 89
- 11.1 – Detailed Description 90
- 12.2 – SPI System Errors 101
- 12.3 – SPI Interrupts 102
- SECTION 13 – 3-WIRE 110
- Using PWMCN and PWMDATA 113
- Core Clock 120
- FrequencyClockPWM 123
- FrequencyFramePWM 123
- * = 01b 127
- MULTIPLIER 140
- SECTION 19 – WATCHDOG TIMER 146
- 20.1 – TAP Controller 150
- 20.2 – TAP State Control 151
- 20.3 – Communication via TAP 152
- 21.2 – Debug Mode 160
- 22.1 – Detailed Description 169
- 22.2 – Bootloader Operation 171
- 22.3 – Bootloader Commands 173
- SECTION 23 – PROGRAMMING 179
- SECTION 24 – INSTRUCTION SET 192
- SECTION 25 – UTILITY ROM 220
- 25.4 – Utility ROM Examples 227
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