
MAX15301 PMBus Command Set User’s Guide
Rev 1 Page 13 of 53
VOUT_TRANSITION_RATE
0x9B33 (0.1V/ms, see Description)
See Section 13.8 of the PMBus Specification Part II.
To achieve output voltage slew-rate control, the MAX15301 has an 8-bit timer with approximately
243ns resolution. When the timer expires, the 12-bit voltage setpoint is incremented or decremented
until the setpoint reaches its final value. This limits the minimum and maximum possible slew-rates
for each feedback divider range as follows:
VOUT_TRANSITION_RATE, kV/s
For each divider range, the minimum transition rate is also the resolution (minimum step size).
The desired value of VOUT_TRANSITION_RATE is retained in memory, regardless of hardware
limitations imposed by the feedback divider range, but the read-back value is
hardware register settings.
If a commanded value of VOUT_TRANSITION_RATE exceeds the maximum possible slew-rate for the
feedback divider range, the MAX15301 sets the slew-rate control timer to zero, and the output
voltage setpoint is updated to the new setpoint value immediately and without delay. In this case,
VOUT_TRANSITION_RATE will read back as 0mV/μs to avoid a divide-by-zero operation.
VOUT_DROOP
See Section 13.9 of the PMBus Specification Part II.
The MAX15301 uses low-pass filtered inductor DCR current-sense information (i.e. the READ_IOUT
signal) to establish the load-line characteristic according to the VOUT_DROOP value. Because of this
low-pass filtering of the load current information, there will be some settling time in the output
voltage positioning when VOUT_DROOP is non-zero.
It is also important to calibrate READ_IOUT using IOUT_CAL_GAIN and IOUT_CAL_OFFSET to achieve
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