Maxim-integrated DS4830A Optical Microcontroller Manuel d'utilisateur Page 105
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DS4830A User’s Guide
105
11.2.3 – I
2
C Slave Interrupt Enable Register (I2CIE_S)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
-
I2CROIE
I2CGCIE
I2CNACKIE
-
I2CAMIE
I2CTOIE
I2CSTRIE
I2CRXIE
I2CTXIE
I2CSRIE
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:10
Reserved
Reserved. The user should not write to these bits.
9
I2CROIE
I
2
C Slave Receiver Overrun Interrupt Enable. Setting this bit to ‘1’ causes an interrupt to the
CPU when a receiver overrun condition is detected (I2ROI=1). Clearing this bit to ‘0’ disables the
receiver overrun detection interrupt.
8
I2CGCIE
I
2
C Slave General Call Interrupt Enable. Setting this bit to '1' causes an interrupt to the CPU
when a general call is detected (I2CGCI=1). Clearing this bit to '0' disables the general call
interrupt.
7
I2CNACKIE
I
2
C
Slave NACK Interrupt Enable. Setting this bit to ‘1’ causes an interrupt to the CPU when a
NACK is detected (I2CNACKI=1). Clearing this bit to ‘0’ disables the NACK detection interrupt.
6
Reserved
Reserved. The user should not write to this bit.
5
I2CAMIE
I
2
C Slave Address Match Interrupt Enable. Setting this bit to ‘1’ causes an interrupt to the CPU
when the I
2
C controller detects
an address that matches the I2CSLA_S value (I2CAMI=1).
Clearing this bit to ‘0’ disables the address match interrupt.
4
I2CTOIE
I
2
C
Slave Timeout Interrupt Enable. Setting this bit to ‘1’ causes an interrupt to the CPU when
an SMBUS timeout condition is detected (I2CTOI=1). Clearing this bit to ‘0’ disables the timeout
interrupt.
3
I2CSTRIE
I
2
C Slave Clock Stretch Interrupt Enable. Setting this bit to '1' generates an interrupt to the CPU
when the clock stretch interrupt flag is set (I2CSTRI=1). Clearing this bit disables the clock stretch
interrupt.
2
I2CRXIE
I
2
C Slave Receive Ready Interrupt Enable. Setting this bit to ‘1’ causes an interrupt to the CPU
when receive ready interrupt flag is set (I2CRXI=1). Clearing this bit to ‘0’ disables the receive
ready interrupt.
1
I2CTXIE
I
2
C Slave Transmit Complete Interrupt Enable. Setting this bit to ‘1’ causes an interrupt to the
CPU when transmit complete interrupt flag is set (I2CTXI=1). Clearing this bit to ‘0’ disables
transmit complete interrupt.
0
I2CSRIE
I
2
C Slave START Interrupt Enable.
Setting this bit to ‘1’ causes an interrupt to the CPU when a
START condition is detected (I2CSRI=1). Clearing this bit to ‘0’ disables the START detection
interrupt.
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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