
DS4830A User’s Guide
42
INTERRUPT INTERRUPT FLAG LOCAL ENABLE BIT
INTERRUPT
IDENTIFICATI
INTERRUPT
IDENTIFICATION
BIT
MODULE
ENABLE
BIT
MIIR5.QT
IIR.II5 IMR.IM5
SPI Master Transfer Complete
SPICF_M.ESPII
MIIR5.SPI_M
SPI Master Write Collision
SPI Master Receive Overrun
When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local,
module, or global level. Interrupt flags must be cleared within the user interrupt routine to avoid repeated interrupts
from the same source. Since all interrupts vector to the address contained in the Interrupt Vector (IV) register, the
Interrupt Identification Register (IIR) may be used by the interrupt service routine to determine the module source of
an interrupt. The IIR contains a bit flag for each peripheral module and one flag associated with all system interrupts;
if the bit for a module is set, then an interrupt is pending that was initiated by that module.
In the DS4830A MIIR registers are defined for module 1, 4, and 5. In these modules the DS4830A provides two ways
to determine which block inside a module (for module 1, 4, and 5 only) caused an interrupt to occur. Module 1, 4
and 5 has Module Interrupt Identification Registers MIIR1, MIIR4 and MIIR5 respectively that indicate which of the
module’s interrupt sources has a pending interrupt. The peripheral register bits inside the module also provide a way
to differentiate among interrupt sources. Section 5.2 has more detail on the Module Interrupt Identification Registers.
The Interrupt Vector (IV) register provides the location of the interrupt service routine. It may be set to any location
within program memory. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different
address, the user program must determine whether a jump to 0000h came from a reset or interrupt source.
5.2 – Module Interrupt Identification Registers
The MIIR registers are implemented to indicate which particular function within a peripheral module has caused the
interrupt. The DS4830A has 6 peripheral modules, M0 through M5. MIIR registers are implemented in peripheral
module 1, 4 and 5. The MIIR registers are 16-bit read-only registers and all of them default to 0000h on system
reset.
Each defined bit in an MIIR register is the final interrupt from a specific function, i.e., the interrupt enable bit(s)
ANDed with the interrupt flag(s). A function can have multiple flags, but they all are ANDed with corresponding
Commentaires sur ces manuels